IEEE-754 compliant Algorithms for Fast Multiplication of Double Precision Floating Point Numbers

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Author(s):
Geetanjali Wasson
Published Date:
September 29, 2011
Issue:
Volume 1, Issue 1
Page(s):
1 - 7
DOI:
10.7815/ijorcs.11.2011.001
Views:
5798
Downloads:
862

Keywords:
csd (canonic signed digit), fpga (field programmable gated array), double precision floating point number
Citation:
Geetanjali Wasson, "IEEE-754 compliant Algorithms for Fast Multiplication of Double Precision Floating Point Numbers". International Journal of Research in Computer Science, 1 (1): pp. 1-7, September 2011. doi:10.7815/ijorcs.11.2011.001 Other Formats

Abstract

In image and signal processing applications floating-point multiplication is major concern in calculations. Performing multiplication on floating point data is a long course of action and requires huge quantity of processing time. By improving the speed of multiplication task overall speed of the system can be enhanced. The Bottleneck in the floating point multiplication process is the multiplication of mantissas which needs 53*53 bit integer multiplier for double precision floating point numbers. By improving the speed of multiplication task the overall speed of the system can be improved. In this paper a comparison on the existing trends in mantissa multiplication is made. Vedic and Canonic Signed digit algorithms were compared on parameters like speed, complexity of routing, pipelining, resource required on FPGA. The comparison showed that Canonic Signed Digit Algorithm is better than Vedic algorithm in terms of speed and resources required on spartan3 FPGA.


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